One key objective of CMP (Chemical Mechanical Polishing) is to thin wafers to the target thickness. This process demands extremely high thickness uniformity, and as manufacturing processes advance, the requirements for thickness control become increasingly stringent. So, what impacts does thickness deviation cause? And how does CMP polishing achieve precise wafer thickness control? These are the topics we will explore today.
Impacts of Wafer Thickness Deviation
In CMP polishing, TTV (Total Thickness Variation) is typically used to measure wafer thickness uniformity. TTV refers to the difference between the maximum and minimum thicknesses across the wafer diameter, and it directly determines chip performance and yield. As process nodes advance to 3nm, 2nm, and beyond, the requirement for wafer surface flatness has jumped from the micrometer level to the sub-nanometer level—even local areas need to be controlled within 0.3nm. Once TTV exceeds the standard, multiple issues arise:
- Lithography Failure: Lithography machines adjust focus based on the wafer surface height. Excessive TTV forces the lithography machine to continuously adjust the focal plane, leading to focusing errors that fail to meet nanoscale patterning requirements. In severe cases, it causes pattern defocus and complete lithography failure.
- Deposition Failure: Both physical vapor deposition (PVD) and chemical vapor deposition (CVD) have strict requirements for TTV. Significant thickness deviation leads to fluctuations in the deposited layer thickness, directly affecting the uniformity of interconnect layer resistance, resulting in signal delay or increased power consumption.
- Device Performance Degradation: Uneven wafer thickness induces mechanical stress, which may reduce carrier mobility in the transistor channel region—impairing device performance. In multi-layer interconnect structures, TTV causes variations in metal layer thickness, altering parasitic capacitance between adjacent wires. This damages high-frequency signal integrity and significantly increases the risk of delay and crosstalk.
- Reduced Chip Lifespan: Wafers with uneven thickness develop localized thermal resistance differences after packaging. For wafers with excessive TTV, the hot-spot temperature in power devices can be 15–20℃ higher than normal areas, accelerating electromigration and thermal fatigue and drastically shortening chip lifespan.
Of course, the impacts of TTV extend far beyond the above. For example, it increases packaging difficulty, reduces mechanical performance, and causes fluctuations in electrical properties. The points above merely serve as an introduction.
How CMP Achieves Precise Wafer Thickness Control
Numerous factors influence wafer thickness during CMP:
- Non-linear Material Removal Rate: The material removal rate during polishing is not constant; instead, it may undergo non-linear changes at any time.
- Interrelated Polishing Parameters: Grinding parameters such as polishing pressure, rotation speed, temperature, and polishing slurry flow rate interact with one another. Any variation in these parameters can lead to thickness unevenness.
- Material Property Differences: Different materials exhibit significant variations in hardness and chemical activity, which inevitably result in thickness differences after polishing.